參數(shù)資料
型號(hào): IDT70V25S35PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
中文描述: 8K X 16 DUAL-PORT SRAM, 35 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù): 11/17頁(yè)
文件大小: 276K
代理商: IDT70V25S35PF
6.39
11
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH
BUSY
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING
(M/
S
= V
IH
)
(1)
2944 drw 14
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/
S
= V
IH
)
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
APS
is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
2944 drw 15
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
2944 drw 13
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(2)
(3)
(1)
NOTES:
1. t
WH
must be met for both
BUSY
input (slave) output master.
2. Busy is asserted on port "B" Blocking R/
W
"B"
, until
BUSY
"B"
goes High.
3. t
WB
is only for the slave version.
相關(guān)PDF資料
PDF描述
IDT70V25L25G HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
IDT70V25L25J HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
IDT70V25L25PF HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
IDT70V25L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
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