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參數(shù)資料
| 型號： | IDT70V261L35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 16K X 16 DUAL-PORT SRAM, 35 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 153K |
| 代理商： | IDT70V261L35PF |
6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
14
The IDT70V261 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V261 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not
selected (
CE
HIGH). When a port is enabled, access to the entire
memory array is permtted.
%
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
3FFE (HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per Truth
Table III. The left port clears the interrupt through access of address
location 3FFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care". Likewise,
the right port interrupt flag (
INT
R
) is asserted when the left port writes
to memory location 3FFF (HEX) and to clear the interrupt flag (
INT
R
),
the right port must read the memory location 3FFF. The message (8
bits) at 3FFE or 3FFF is user-defined since it is an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE
and 3FFF are not used as mail boxes, but as part of the randomaccess
memory. Refer to Truth Table III for the interrupt operation.
.B
Busy Logic provides a hardware indication that both ports of the
RAMhave accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAMis
“
busy
”
. The
BUSY
pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted fromthe side that receives a
BUSY
indication, the write
signal is gated internally to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the
BUSY
outputs
together and use any busy indication as an interrupt source to flag an
illegal or illogical operation. If the write inhibit function of
BUSY
logic
is not desirable, the
BUSY
logic can be disabled by placing the part in
slave mode with the M/
S
pin. Once in slave mode the
BUSY
pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the
BUSY
pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the
BUSY
pin for
that port LOW.
The
BUSY
outputs on the IDT70V261 RAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the
BUSY
indication
for the resulting array requires the use of an external AND gate.
*(#4;#.B
)'-3.
When expanding an IDT70V261 RAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAM
array will receive a
BUSY
indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the
BUSY
signal as a write inhibit signal. Thus on the
IDT70V261 SRAMthe
BUSY
pin is an output if the part is used as a
master (M/
S
pin = V
IH
), and the
BUSY
pin is an input if the part used
as a slave (M/
S
pin = V
IL
) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating
BUSY
on one side
of the array and another master indicating
BUSY
on one other side of
the array. This would inhibit the write operations fromone port for part
of a word and inhibit the write operations fromthe other port for part of
the other word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a
BUSY
flag to be output fromthe master before the
actual write pulse can be initiated with either the R/
W
signal or the byte
enables. Failure to observe this timng can result in a glitched internal
write inhibit signal and corrupted data in the slave.
'#
The IDT70V261 is a fast Dual-Port 16K x 16 CMOS Static RAMwith
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-
Port SRAMto claima privilege over the other processor for functions
defined by the systemdesigner
’
s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAMor any other shared
resource.
The Dual-Port SRAMfeatures a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAMand can
be read from or written to, at the same time with the only possible
conflict arising fromthe simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
systemprogramto avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by
CE
, the Dual-Port SRAMenable, and
SEM
, the
semaphore enable. The
CE
and
SEM
pins control on-chip power down
circuitry that permts the respective port to go into standby mode when
not selected. This is the condition which is shown in Truth Table I where
CE
and
SEM
are both HIGH.
3040 drw 17
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
,
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V261 RAMs.
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| IDT70V261L35PF8 | 功能描述:IC SRAM 256KBIT 35NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V261L55PF | 功能描述:IC SRAM 256KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V261L55PF8 | 功能描述:IC SRAM 256KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V261S25PF | 功能描述:IC SRAM 256KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V261S25PF8 | 功能描述:IC SRAM 256KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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