參數(shù)資料
型號: IDT70V261S55PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
中文描述: 16K X 16 DUAL-PORT SRAM, 55 ns, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 16/17頁
文件大小: 153K
代理商: IDT70V261S55PF
6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
16
longer needs the resource, the entire systemcan hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timng is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programmng technique, if semaphores
are msused or msinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization programat power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into themat
initialization fromboth sides to assure that they will be free when
needed.
<'#@'4
Perhaps the simplest application of semaphores is their applica-
tion as resource markers for the IDT70V261
s Dual-Port RAM. Say the
16K x 16 RAMwas to be divided into two 8K x 16 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of Dual-Port RAM
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 8K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read back a one
in response to the zero it had attempted to write into Semaphore 0. At
this point, the software could choose to try and gain control of the
second 8K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and performother tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a simlar task with Semaphore 0, this protocol would allow the
two processors to swap 8K blocks of Dual-Port RAMwith each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port RAMor other shared resources into eight parts. Sema-
phores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful formof arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determned
which memory area was
off-limts
to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
WAIT
state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAMsegments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
相關PDF資料
PDF描述
IDT70V261S55PFI HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L25G HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L25GI HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L25J HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L25JI HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
相關代理商/技術參數(shù)
參數(shù)描述
IDT70V261S55PF8 功能描述:IC SRAM 256KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口,異步 存儲容量:128K(8K x 16) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP(14x14) 包裝:托盤 其它名稱:70V25S15PF
IDT70V26L25G 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 25NS 84PGA
IDT70V26L25J 功能描述:IC SRAM 256KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口,同步 存儲容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V26L25J8 功能描述:IC SRAM 256KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口,同步 存儲容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
IDT70V26L25JI 功能描述:IC SRAM 256KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口,同步 存儲容量:1.125M(32K x 36) 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA(17x17) 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8