參數(shù)資料
型號(hào): IDT70V26L35GI
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
中文描述: 高速3.3 16K的× 16 DUAL-PORT靜態(tài)RAM
文件頁(yè)數(shù): 11/17頁(yè)
文件大小: 144K
代理商: IDT70V26L35GI
6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2945 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
/%2;%
2$+)34*
=A!
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Waveformof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
t
WP
(actual) or t
DDD
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
$-;-%..*++
BUSY
>7!
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(SLAVE).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(SLAVE), then
BUSY
is an input (
BUSY
"A"
= V
IH
and
BUSY
"B"
= "don't care", for this example).
5. All timng is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite fromport "A".
70V26X25
Com'l Only
70V26X35
Com'l Only
70V26X55
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
25
____
35
____
45
ns
t
BDA
BUSY
Disable Time fromAddress Not Match
____
25
____
35
____
45
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
25
____
35
____
45
ns
t
BDC
BUSY
Disable Time fromChip Enable High
____
25
____
35
____
45
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
40
____
50
ns
t
WH
Write Hold After
BUSY
(5)
20
____
25
____
25
____
ns
BUSY
INPUT TIMING (M/
S
= VIL)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
55
____
65
____
85
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
50
____
60
____
80
ns
2945 tbl 13
相關(guān)PDF資料
PDF描述
IDT70V26L35J HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L35JI HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L55G HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L55GI HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
IDT70V26L55J HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
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