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參數(shù)資料
| 型號(hào)： | IDT70V26L55G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 16K X 16 DUAL-PORT SRAM, 55 ns, CPGA84 |
| 封裝： | CERAMIC, PGA-84 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | IDT70V26L55G |
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6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
write operations can be prevented to a port by tying the
BUSY
pin for
that port LOW.
The
BUSY
outputs on the IDT 70V26 RAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the
BUSY
indication
for the resulting array requires the use of an external AND gate.
-+%1%
0,);/3
When expanding an IDT70V26 RAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAM
array will receive a
BUSY
indication, and to output that indication. Any
BUSY
B
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAMand can
be read from or written to, at the same time with the only possible
conflict arising fromthe simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
systemprogramto avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
down feature controlled by
CE
, the Dual-Port SRAMenable, and
SEM
,
the semaphore enable. The
CE
and
SEM
pins control on-chip power
down circuitry that permts the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where
CE
and
SEM
are both HIGH.
Systems which can best use the IDT70V26 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit froma performance increase offered by the IDT70V26's
hardware semaphores, which provide a lockout mechanismwithout
requiring complex programmng.
Software handshaking between processors offers the maximumin
systemflexibility by permtting shared resources to be allocated in
varying configurations. The IDT70V26 does not use its semaphore
flags to control any resources through hardware, thus allowing the
systemdesigner total flexibility in systemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
9%)%-
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, fromone port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called
“
Token Passing Allocation.
”
In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determnes that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore
’
s status or remove its request for that semaphore to
performanother task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V26 in a
separate memory space fromthe Dual-Port SRAM. This address
space is accessed by placing a LOW input on the
SEM
pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address,
OE
, and R/
W
) as they would be used in accessing a
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V26 RAMs.
number of slaves to be addressed in the same address range as the
master use the
BUSY
signal as a write inhibit signal. Thus on the
IDT70V26 SRAMthe
BUSY
pin is an output if the part is used as a
master (M/
S
pin = H), and the
BUSY
pin is an input if the part used as
a slave (M/
S
pin = L) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating
BUSY
on one side
of the array and another master indicating
BUSY
on one other side of
the array. This would inhibit the write operations fromone port for part
of a word and inhibit the write operations fromthe other port for word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a
BUSY
flag to be output fromthe master before the
actual write pulse can be initiated with either the R/
W
signal or the byte
enables. Failure to observe this timng can result in a glitched internal
write inhibit signal and corrupted data in the slave.
)%
The IDT70V26 is an extremely fast Dual-Port 16K x 16 CMOS
Static RAMwith an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAMto claima privilege over the other
processor for functions defined by the systemdesigner
’
s software. As
an example, the semaphore can be used by one processor to inhibit
the other fromaccessing a portion of the Dual-Port SRAMor any other
shared resource.
The Dual-Port SRAMfeatures a fast access time, and both ports
2945 drw 16
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V26L55GI | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26L55J | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26L55JI | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26S | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| IDT70V26S25G | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V26L55J | 功能描述:IC SRAM 256KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V26L55J8 | 功能描述:IC SRAM 256KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V26S25J | 功能描述:IC SRAM 256KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V26S25J8 | 功能描述:IC SRAM 256KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V26S35G | 功能描述:IC SRAM 256KBIT 35NS 84PGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
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