參數(shù)資料
型號(hào): IDT70V28L20PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM
中文描述: 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 11/17頁(yè)
文件大?。?/td> 152K
代理商: IDT70V28L20PF
11
IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4849 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
)8;8=4::''
BUSY
%7
S
-,
52
#
!!/#
)8;8=4
BUSY
%7
S
-,
5@
#
NOTES:
1. t
WH
must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
3. t
WB
is only for the 'slave' version.
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(SLAVE).
2.
CE
L
=
CE
R
= V
IL,
refer to Chip Enable Truth Table.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timng is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite fromport "A".
4849 drw 12
R/
W
"A"
BUSY
"B"
t
WB
(3)
R/
W
"B"
t
WH
(1)
(2)
t
WP
相關(guān)PDF資料
PDF描述
IDT70V28L20PFI HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM
IDT70V3389S6BC HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3389S6BCI HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3389S6BF HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3389S6BFI HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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