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參數(shù)資料
| 型號(hào)： | IDT70V3389S6PRFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 64K X 18 DUAL-PORT SRAM, 6 ns, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 176K |
| 代理商： | IDT70V3389S6PRFI |
6.42
IDT70V3389S
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
CLK
L
R/
W
L
ADDRESS
L
DATA
INL
CLK
R
R/
W
R
ADDRESS
R
DATA
OUTR
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
MNO
MATCH
MATCH
VALID
4832 drw 08
t
DC
R/
W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
4832 drw 09
Qn
Qn + 3
DATA
OUT
CE
1
UB
,
LB
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ
NOP
READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
&,8,*'*
#
NOTES:
1.
CE
0
,
UB
,
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
CNTRST
= V
IH
.
2.
OE
= V
IL
for the Right Port, which is being read from
OE
= V
IH
for the Left Port, which is being written to.
3. If t
CO
< mnimumspecified, then data fromright port read is not valid until following right port clock cycle (ie, time fromwrite to valid read on opposite port will
be t
CO
+ 2 t
CYC2
+ t
CD2
). If t
CO
> mnimum then data fromright port read is available on first right port clock cycle (ie, time fromwrite to valid read on opposite
port will be t
CO
+ t
CYC
+ t
CD2
).
&,8**AA,AA*
OE
92
#
#
NOTES:
1. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
2.
CE
0
,
UB
,
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
CNTRST
= V
IH
. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V3389S | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3389S4BC | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3389S4BCI | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3389S4BF | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3389S4BFI | HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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