參數(shù)資料
型號(hào): IDT70V3569S5BC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述: 16K X 36 DUAL-PORT SRAM, 5 ns, PBGA256
封裝: BGA-256
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 198K
代理商: IDT70V3569S5BC
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
ADDRESS
An
CLK
DATA
OUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
4831 drw 11
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATA
IN
Dn + 3
Dn + 2
CE
0
CLK
4831 drw 10
DATA
OUT
Qn
Qn + 4
CE
1
BE
n
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ
WRITE
READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
&,8**3'***8
#
NOTES:
1.
CE
0
,
OE
,
BE
n
= V
IL
; CE
1
, R/
W
, and
CNTRST
= V
IH
.
2. If there is no address change via
ADS
= V
IL
(loading a new address) or
CNTEN
= V
IL
(advancing the address), i.e.
ADS
= V
IH
and
CNTEN
= V
IH
, then
the data output remains constant for subsequent clocks.
&,8 **AA,AA*
OE
*#
#
NOTES:
1. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
2.
CE
0
,
BE
n
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
CNTRST
= V
IH
.
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timng does not meet requirements for fastest speed grade. This waveformindicates how logically it could be done if timng so allows.
相關(guān)PDF資料
PDF描述
IDT70V3569S5BCI HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3569S5BF HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3569S5BFI HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3569S5DRI HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3569S6BC HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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