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參數(shù)資料
| 型號(hào)： | IDT70V3569S5BCI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 16K X 36 DUAL-PORT SRAM, 5 ns, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 198K |
| 代理商： | IDT70V3569S5BCI |
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6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS
,
CNTEN
,
CNTRST
= V
IH
.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
&'&()*+,*-(
! "#
.
Left Port
Right Port
Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/O
35L
I/O
0R
- I/O
35R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
BE
0L
-
BE
3L
BE
0R
-
BE
3R
Byte Enables (9-bit bytes)
V
DDQL
V
DDQR
Power (I/O Bus)
(3.3V or 2.5V)
(1)
OPT
L
OPT
R
Option for selection V
DDQX
(1,2)
V
DD
Power
(3.3V)
(1)
V
SS
Ground
(0V)
4831 tbl 01
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/
W
Byte 3
I/O
27-35
Byte 2
I/O
18-26
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
↑
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
High-Z
High-Z
High-Z
D
IN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
High-Z
High-Z
D
IN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
High-Z
D
IN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
D
IN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
High-Z
High-Z
D
IN
D
IN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
D
IN
D
IN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
High-Z
High-Z
High-Z
D
OUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
High-Z
High-Z
D
OUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
High-Z
D
OUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
D
OUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
High-Z
High-Z
D
OUT
D
OUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
D
OUT
D
OUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
↑
L
H
L
L
L
L
X
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
4831 tbl 02
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX
must be supplied
at 2.5V. The OPT pins are independent of one another
—
both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V3569S5BF | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3569S5BFI | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3569S5DRI | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3569S6BC | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V3569S6BCI | HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V3569S5BCI8 | 功能描述:IC SRAM 576KBIT 5NS 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V3569S5BF | 功能描述:IC SRAM 576KBIT 5NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V3569S5BF8 | 功能描述:IC SRAM 576KBIT 5NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V3569S5BFI | 功能描述:IC SRAM 576KBIT 5NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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