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參數(shù)資料
| 型號： | IDT70V7599S-200DR |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速與3.3V 3.3V的128K的× 36 SYNCHRONOU開戶銀行可切換雙端口靜態(tài)RAM或2.5V的接口 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 489K |
| 代理商： | IDT70V7599S-200DR |
6.42
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
BA
0L
- BA
5L
BA
0R
- BA
5R
Bank Address
(4)
A
0L
- A
10L
A
0R
- A
10R
Address
I/O
0L
- I/O
35L
I/O
0R
- I/O
35R
Data Input/Output
CLK
L
CLK
R
Clock
PL/
FT
L
PL/
FT
R
Pipeline/Flow-Through
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
REPEAT
L
REPEAT
R
Counter Repeat
(3)
BE
0L
-
BE
3L
BE
0R
-
BE
3R
Byte Enables (9-bit bytes)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(1)
OPT
L
OPT
R
Option for selecting V
DDQX
(1,2)
V
DD
Power (3.3V)
(1)
V
SS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5626 tbl 01
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA
0L
- BA
5L
≠
BA
0R
- BA
5R
). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70V7599S200BC | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S200BCI | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S200BF | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S133BC | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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