參數(shù)資料
型號: IDT70V9089L9PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
中文描述: 64K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù): 3/19頁
文件大小: 332K
代理商: IDT70V9089L9PF
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
3
Truth Table II—Address Counter Control
(1,2,3)
Previous
Internal
Address
Used
CLK
Truth Table I—Read/Write and
Enable Control
(1,2,3)
OE
CLK
CE
0
CE
1
R/
W
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS
,
CNTEN
,
CNTRST
= X.
3.
OE
is an asynchronous input signal.
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
15L
(1)
A
0R
- A
15R
(1)
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT
/PIPE
L
FT
/PIPE
R
Flow-Through/Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
3750 tbl 01
I/O
0-7
Mode
X
H
X
X
High-Z
Deselected - Power Down
X
X
L
X
High-Z
Deselected - Power Down
X
L
H
L
DATA
IN
Write
L
L
H
H
DATA
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
3750 tbl 02
External
Address
Internal
Address
ADS
CNTEN
CNTRST
I/O
(3)
MODE
An
X
An
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
H
H
H
D
I/O
(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
X
A
0
X
X
L
(4)
D
I/O
(0)
Counter Reset to Address 0
3750 tbl 03
NOTE:
1. A
15
X
is a NC for ID70V9079.
2.
LB
and
UB
are single buffered regardless of state of
FT
/PIPE.
3.
CE
o and CE
1
are single buffered when
FT
/PIPE = V
IL
,
CE
o and CE
1
are double buffered when
FT
/PIPE = V
IH
,
i.e. the signals take two cycles to deselect.
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/
W
= V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
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