參數(shù)資料
型號(hào): IDT70V9279L7PRF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM
中文描述: 32K X 16 DUAL-PORT SRAM, 18 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁(yè)數(shù): 12/19頁(yè)
文件大?。?/td> 337K
代理商: IDT70V9279L7PRF
6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,3,5)
12
DATA
IN "A"
CLK
"B"
R/
W
"B"
ADDRESS
"A"
R/
W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD1
t
DC
DATA
OUT "B"
3743 drw 09
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
HA
t
CD1
t
CCS
t
DC
t
SA
t
SW
(4)
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2.
CE
0
,
UB
,
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
CNTRST
= V
IH
.
3.
OE
= V
IL
for the Right Port, which is being read from.
OE
= V
IH
for the Left Port, which is being written to.
4. If t
CCS
< maximum specified, then data from right port READ is not valid until the maximum specified for t
CWDD
.
If t
CCS
> maximum specified, then data from right port READ is not valid until t
CCS
+ t
CD1
. t
CWDD
does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
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