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參數(shù)資料
| 型號： | IDT71256L85Y |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-SO -20 to 85 |
| 中文描述： | 的CMOS靜態(tài)RAM 256K（32K的× 8位） |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 78K |
| 代理商： | IDT71256L85Y |
7.2
4
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2946 tbl 08
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
*Includes scope and jig capacitances
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V
LC
= 0.2V, V
HC
= V
CC
– 0.2V
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
V
DR
I
CCDR
Parameter
Test Condition
Min.
2.0
—
—
0
2.0v
—
—
—
—
3.0V
—
—
—
—
2.0V
—
500
120
—
3.0V
—
800
200
—
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
—
MIL.
COM’L.
t
CDR
Chip Deselect to Data
Retention Time
Operation Recovery Time
CS
≥
V
HC
ns
t
R(3)
t
RC(2)
—
—
—
—
ns
NOTES:
1. T
A
= +25
°
C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed, but not tested.
2946 tbl 10
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT71256S
Typ.
IDT71256L
Min.
Symbol
Parameter
Test Condition
Min.
Max.
Typ.
Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max.,
V
IN
= GND to V
CC
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
μ
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
μ
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
—
—
0.4
0.5
—
—
—
—
0.4
0.5
V
—
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
2.4
—
—
2.4
—
—
V
2946 tbl 09
2946 drw 05
480
5pF*
255
DATA
OUT
5V
2946 drw 04
480
30pF*
255
DATA
OUT
5V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71256S | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S100D | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-TSSOP -20 to 85 |
| IDT71256S100DB | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S100L | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-TSSOP -20 to 85 |
| IDT71256S100LB | Dual-Channel Pulse-Width-Modulation (PWM) Control Circuit 16-TSSOP -20 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71256S100DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 100NS 28CDIP |
| IDT71256S100DBRT | 制造商:Integrated Device Technology Inc 功能描述:71256S100DBRT |
| IDT71256S100TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 100NS 28CDIP |
| IDT71256S20Y | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT71256S25DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 25NS 28CDIP |
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