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參數(shù)資料
| 型號(hào)： | IDT71256S120Y |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS STATIC RAM 256K (32K x 8-BIT) |
| 中文描述： | 的CMOS靜態(tài)RAM 256K（32K的× 8位） |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | IDT71256S120Y |
7.2
8
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±
200mV from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified t
WP.
For a
CS
controlled write cycle,
OE
may be LOW with no degradation to t
CW
.
CS
2946 drw 10
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
DATA
OUT
t
WHZ
t
OW
(4)
(7)
t
AS
(6)
(4)
t
OHZ
(6)
OE
t
DH
t
CS
2946 drw 11
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH2
t
AS
t
WR
(7)
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