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參數(shù)資料
| 型號： | IDT71256S30D |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Single UART Without FIFO 44-PLCC |
| 中文描述： | 32K X 8 STANDARD SRAM, 30 ns, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT71256S30D |
7.2
7
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±
200mV from steady state.
2946 drw 07
ADDRESS
CS
DATA
OUT
t
RC
t
AA
t
OH
t
ACS
(5)
t
CLZ
t
CHZ(5)
t
OE
t
OLZ
(5)
t
OHZ(5)
OE
2946 drw 08
ADDRESS
t
RC
t
AA
t
OH
t
OH
DATA
OUT
2946 drw 09
DATA
OUT
CS
t
ACS
(5)
t
CLZ
(5)
t
CHZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71256S30DB | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S30L | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S30LB | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S30P | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S30PB | Single UART with Parallel Port And Without FIFO 68-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71256S35DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 35NS 28CDIP |
| IDT71256S35DM | 制造商:Integrated Device Technology Inc 功能描述:71256S35DM |
| IDT71256S35TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 35NS 28CDIP |
| IDT71256S45DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 45NS 28CDIP |
| IDT71256S45TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 28CDIP |
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