參數(shù)資料
型號(hào)： IDT71256S35PB
廠商： Integrated Device Technology, Inc.
英文描述： CMOS STATIC RAM 256K (32K x 8-BIT)
中文描述： 的CMOS靜態(tài)RAM 256K（32K的× 8位）
文件頁(yè)數(shù)： 5/9頁(yè)
文件大小： 78K
代理商： IDT71256S35PB
7.2
5
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW V
CC
DATA RETENTION WAVEFORM
2946 drw 06
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
≥
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
71256S25
71256L25
71256S30
(3)
71256L30
(3)
71256S35
71256L35
71256S45
71256L45
71256L20
(1)
Symbol
Parameter
Min.
Max.
Min. Max.
Min.
Max.
Min.
Max.
Min. Max. Unit
Read Cycle
t
RC
Read Cycle Time
20
—
25
—
30
—
35
—
45
—
ns
t
AA
Address Access Time
—
20
—
25
—
30
—
35
—
45
ns
t
ACS
Chip Select Access Time
—
20
—
25
—
30
—
35
—
45
ns
t
CLZ
(2)
Chip Select to Output in Low-Z
5
—
5
—
5
—
5
—
5
—
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
—
10
—
11
—
15
—
15
—
20
ns
t
OE
Output Enable to Output Valid
—
10
—
11
—
13
—
15
—
20
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
2
—
2
—
2
—
2
—
0
—
ns
t
OHZ
(2)
Output Disable to Output in High-Z
2
8
2
10
2
12
2
15
—
20
ns
t
OH
Output Hold from Address Change
5
—
5
—
5
—
5
—
5
—
ns
Write Cycle
t
WC
Write Cycle Time
20
—
25
—
30
—
35
—
45
—
ns
t
CW
Chip Select to End-of-Write
15
—
20
—
25
—
30
—
40
—
ns
t
AW
Address Valid to End-of-Write
15
—
20
—
25
—
30
—
40
—
ns
t
AS
Address Set-up Time
0
—
0
—
0
—
0
—
0
—
ns
t
WP
Write Pulse Width
15
—
20
—
25
—
30
—
35
—
ns
t
WR
Write Recovery Time
0
—
0
—
0
—
0
—
0
—
ns
t
DW
Data to Write Time Overlap
11
—
13
—
14
—
15
—
20
—
ns
t
WHZ
(2)
Write Enable to Output in High-Z
—
10
—
11
—
15
—
15
—
20
ns
t
DH
Data Hold from Write Time
0
—
0
—
0
—
0
—
0
—
ns
t
OW
(2)
Output Active from End-of-Write
5
—
5
—
5
—
5
—
5
—
ns
NOTES:
1. 0
°
to +70
°
C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55
°
to +125
°
C temperature range only.
2946 tbl 11
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