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參數(shù)資料
| 型號： | IDT71256S45D |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Replaced by TL16C550C : Single UART with 16-Byte FIFOs 44-PLCC -40 to 85 |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT71256S45D |
7.2
6
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
71256S55
(1)
71256L55
(1)
71256S70
(1)
71256L70
(1)
71256S85
(1)
71256L85
(1)
71256S100
(1,3)
71256L100
(1,3)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
55
—
70
—
85
—
100
—
ns
t
AA
Address Access Time
—
55
—
70
—
85
—
100
ns
t
ACS
Chip Select Access Time
—
55
—
70
—
85
—
100
ns
t
CLZ
(2)
t
CHZ
(2)
Chip Deselect to Output in Low-Z
5
—
5
—
5
—
5
—
ns
Output Enable to Output in Low-Z
—
25
—
30
—
35
—
40
ns
t
OE
Output Enable to Output Valid
—
25
—
30
—
35
—
40
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
0
—
0
—
0
—
0
—
ns
t
OHZ
(2)
Output Disable to Output in High-Z
0
25
0
30
—
35
—
40
ns
t
OH
Output Hold from Address Change
5
—
5
—
5
—
5
—
ns
Write Cycle
t
WC
Write Cycle Time
55
—
70
—
85
—
100
—
ns
t
CW
Chip Select to End-of-Write
50
—
60
—
70
—
80
—
ns
t
AW
Address Valid to End-of-Write
50
—
60
—
70
—
80
—
ns
t
AS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
t
WP
Write Pulse Width
40
—
45
—
50
—
55
—
ns
t
WR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
t
DW
Data to Write Time Overlap
25
—
30
—
35
—
40
—
ns
t
DH
Data Hold from Write Time (
WE
)
0
—
0
—
0
—
0
—
ns
t
WHZ
(2)
Write Enable to Output in High-Z
—
25
—
30
—
35
—
40
ns
t
OW
(2)
Output Active from End-of-Write
5
—
5
—
5
—
5
—
ns
NOTES:
1. –55
°
C to +125
°
C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. Also available: 120 and 150 ns military devices.
2946 tbl 11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71256S45DB | Replaced by TL16C550C : Single UART with 16-Byte FIFOs 48-LQFP -40 to 85 |
| IDT71256S45L | Replaced by TL16C550C : Single UART with 16-Byte FIFOs 40-PDIP 0 to 70 |
| IDT71256S45LB | Replaced by TL16C550C : Single UART with 16-Byte FIFOs 48-LQFP 0 to 70 |
| IDT71256S45P | CMOS STATIC RAM 256K (32K x 8-BIT) |
| IDT71256S45PB | Single UART with 16-Byte FIFOs and Auto Flow Control 44-PLCC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71256S45DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 45NS 28CDIP |
| IDT71256S45TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 28CDIP |
| Idt71256S55DB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 55NS 28CDIP |
| IDT71256S55P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT71256S55TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 256KBIT 55NS 28CDIP |
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