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參數(shù)資料
| 型號： | IDT7130SA35CGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM |
| 中文描述： | 高速每1000 × 8雙端口靜態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7130SA35CGI |
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(7)
12
NOTES:
1.
2.
3.
4.
5.
6.
7.
PLCC, TQFP and STQFP packages only.
Port-to-port delay through RAMcells fromthe writing port to the reading port, refer to “Timng Waveformof Write with Port -to-Port Read and
BUSY
."
To ensure that the earlier of the two ports wins.
t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
'X' in part numbers indicates power rating (S or L).
7130X20
(1)
7140X20
(1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Mlitary
7130X35
7140X35
Com'l
& Mlitary
Symbol
Parameter
Mn.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY
TIMING (For MASTER IDT 7130)
t
BAA
BUSY
Access Time fromAddress
____
20
____
20
____
20
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
20
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
20
____
20
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
20
____
20
ns
t
WH
Write Hold After
BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
30
____
35
____
35
ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(4)
____
25
____
35
____
35
ns
BUSY
INPUT TIMING (For SLAVE IDT 7140)
t
WB
Write to
BUSY
Input
(5)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
30
____
35
____
35
ns
2689 tbl 11a
7130X55
7140X55
Com'l, Ind
& Mlitary
7130X100
7140X100
Com'l, Ind
& Mlitary
Symbol
Parameter
Min.
Max.
Mn.
Max.
Unit
BUSY
TIMING (For MASTER IDT 7130)
t
BAA
BUSY
Access Time fromAddress]
____
30
____
50
ns
t
BDA
BUSY
Disable Time fromAddress
____
30
____
50
ns
t
BAC
BUSY
Access Time fromChip Enable
____
30
____
50
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
30
____
50
ns
t
WH
Write Hold After
BUSY
(6)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100
ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(4)
____
55
____
65
ns
BUSY
INPUT TIMING (For SLAVE IDT 7140)
t
WB
Write to
BUSY
Input
(5)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(6)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100
ns
2689 tbl 11b
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| IDT7130SA35FG | HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM |
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