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參數(shù)資料
| 型號(hào)： | IDT7132LA20FB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速2K × 8雙端口靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 175K |
| 代理商： | IDT7132LA20FB |
6.02
7
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
W
CONTROLLED TIMING)
(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CE
CONTROLLED TIMING)
(1,5)
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of
CE
=
V
IL
and R/
W
=
V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
t
WC
ADDRESS
OE
CE
R/
W
DATA
OUT
DATA
IN
t
AS
t
OW
t
DW
t
DH
t
AW
t
WP(2)
t
HZ
(4)
(4)
t
WZ
t
HZ
2692 drw 09
(6)
(7)
(7)
(3)
(7)
t
WR
t
WC
ADDRESS
CE
R/
W
DATA
IN
t
AS
t
EW
t
WR
t
DW
t
DH
t
AW
2692 drw 10
(6)
(2)
(3)
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|---|---|
| IDT7132LA20J | 功能描述:IC SRAM 16KBIT 20NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) 其它名稱:71V67703S75PFGI |
| IDT7132LA20J8 | 功能描述:IC SRAM 16KBIT 20NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) 其它名稱:71V67703S75PFGI |
| IDT7132LA20JG | 功能描述:IC SRAM 16KBIT 20NS 52PLCC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT7132LA20JG | 制造商:INTEGRATED DEVICE TECHNOLOGY 功能描述:DUAL PORT SRAM 16K 7132 PLCC52 |
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