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參數(shù)資料
| 型號： | IDT7132LA35L48B |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 35 ns, CQCC48 |
| 封裝： | 0.570 X 0.570 INCH, 0.680 INCH HEIGHT, LCC-48 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 175K |
| 代理商： | IDT7132LA35L48B |
6.02
7
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
W
CONTROLLED TIMING)
(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CE
CONTROLLED TIMING)
(1,5)
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of
CE
=
V
IL
and R/
W
=
V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
t
WC
ADDRESS
OE
CE
R/
W
DATA
OUT
DATA
IN
t
AS
t
OW
t
DW
t
DH
t
AW
t
WP(2)
t
HZ
(4)
(4)
t
WZ
t
HZ
2692 drw 09
(6)
(7)
(7)
(3)
(7)
t
WR
t
WC
ADDRESS
CE
R/
W
DATA
IN
t
AS
t
EW
t
WR
t
DW
t
DH
t
AW
2692 drw 10
(6)
(2)
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT7132LA35P | 功能描述:IC SRAM 16KBIT 35NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7132LA35PDG | 功能描述:IC SRAM 16KBIT 35NS 48DIP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7132LA55C | 功能描述:IC SRAM 16KBIT 55NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7132LA55CB | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 55NS SB48 |
| IDT7132LA55FB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 55NS 48FPACK |
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