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參數(shù)資料
| 型號(hào)： | IDT7132LA55F |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, CQFP48 |
| 封裝： | 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, CERAMIC, FP-48 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | IDT7132LA55F |
6.02
5
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(3)
7132X20
(2)
7132X25
(5)
7132X35
7142X35
7132X55
7142X55
7132X100
7142X100
7142X25
(5)
Min. Max. Min.
Symbol
Parameter
Min. Max.
Max. Min. Max. Min.
Max. Unit
Read Cycle
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0
°
C to +70
°
C temperature range. PLCC package only.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time
(1,4)
Output High-Z Time
(1,4)
Chip Enable to Power Up Time
(4)
Chip Disable to Power Down Time
(4)
20
—
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
0
—
0
—
—
25
25
12
—
—
10
—
25
35
—
—
—
3
0
—
0
—
—
35
35
20
—
—
15
—
35
55
—
—
—
3
5
—
0
—
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
0
—
—
100
100
40
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
0
—
0
—
2689 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1)
NOTES:
1. R/
W
= V
IH,
CE
= V
IL,
and is
OE
= V
IL.
Address is valid prior to the coincidental with
CE
transition Low.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations,
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2692 drw 07
t
BDDH
(2,3)
BUSY
OUT
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| IDT7132SA100F | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| IDT7132SA100FB | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| IDT7132SA100J | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| IDT7132SA100JB | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| IDT7132SA100L48 | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7132LA55FB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 55NS 48FPACK |
| IDT7132LA55J | 功能描述:IC SRAM 16KBIT 55NS 52PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT7132LA55J8 | 功能描述:IC SRAM 16KBIT 55NS 52PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7132LA55L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 55NS 48LCC |
| IDT7132LA55P | 功能描述:IC SRAM 16KBIT 55NS 48DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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