參數(shù)資料
型號: IDT7132SA100L48
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
中文描述: 2K X 8 DUAL-PORT SRAM, 100 ns, CQCC48
封裝: 0.570 X 0.570 INCH, 0.680 INCH HEIGHT, LCC-48
文件頁數(shù): 9/11頁
文件大?。?/td> 175K
代理商: IDT7132SA100L48
6.02
9
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY
R
2692 drw 12
R/
W
L
t
WP
t
WH
t
WB
R/
W
R
(2)
(1)
TIMING WAVEFORM OF WRITE WITH
BUSY
(3)
NOTES:
1. t
WH
must be met for both
BUSY
Input (IDT7142, slave) or Output (IDT7132, master).
2.
BUSY
is asserted on port 'B' blocking R/
W
'B', until
BUSY
'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING
(1)
t
APS
ADDR
'A'
and
'B'
ADDRESSES MATCH
t
BAC
t
BDC
CE
'B'
CE
'A'
BUSY
'A'
2692 drw 13
(2)
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
(1)
BUSY
'B'
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
ADDR
'A'
ADDR
'B'
2692 drw 14
(2)
t
BAA
t
BDA
t
RC
or
t
WC
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted (7132 only).
相關PDF資料
PDF描述
IDT7132SA100L48B HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
IDT7132SA100P HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
IDT7132SA100PB HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
IDT7132SA25C HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
IDT7132SA25CB HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
相關代理商/技術參數(shù)
參數(shù)描述
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