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參數(shù)資料
| 型號： | IDT7132SA55JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 255K |
| 代理商： | IDT7132SA55JB |
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(3,5)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(2)
7142X20
(2)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35
ns
t
AOE
Output Enable Access Time
____
11
____
12
____
20
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,4)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,4)
____
10
____
10
____
15
ns
t
PU
Chip Enable to Power Up Time
(4)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(4)
____
20
____
25
____
35
ns
2692 tbl 08a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
55
____
100
____
ns
t
AA
Address Access Time
____
55
____
100
ns
t
ACE
Chip Enable Access Time
____
55
____
100
ns
t
AOE
Output Enable Access Time
____
25
____
40
ns
t
OH
Output Hold from Address Change
3
____
10
____
ns
t
LZ
Output Low-Z Time
(1,4)
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,4)
____
25
____
40
ns
t
PU
Chip Enable to Power Up Time
(4)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(4)
____
50
____
50
ns
2692 tbl 08b
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| IDT7132SA55JI | 功能描述:IC SRAM 16KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| IDT7132SA55L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 55NS 48LCC |
| IDT7132SA55P | 功能描述:IC SRAM 16KBIT 55NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7132SA70P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7133LA20G | 功能描述:IC SRAM 32KBIT 20NS 68PGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
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