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參數(shù)資料
| 型號(hào)： | IDT7134LA45J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 30V Dual Notebook Power Supply N-Channel PowerTrench in SO-14 Package; Package: SO-14; No of Pins: 14; Container: Tape & Reel |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 45 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | IDT7134LA45J |
6.04
7
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(6)
(CONT'D)
7134X45
Min.
7134X55
Min.
7134X70
Min.
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
Parameter
Max.
Max.
Max.
Unit
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write RecoveryTime
Data Valid to End-of-Write
Output High-Z Time
(1, 2)
Data Hold Time
(3)
Write Enabled to Output in High-Z
(1, 2)
45
40
40
0
40
0
20
—
—
—
—
—
—
—
55
50
50
0
50
0
25
—
—
—
—
—
—
—
70
60
60
0
60
0
30
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
t
HZ
—
20
—
25
—
30
ns
t
DH
3
—
3
—
3
—
ns
t
WZ
—
20
—
25
—
30
ns
t
OW
Output Active from End-of-Write
(1, 2, 3)
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4)
3
—
3
—
3
—
ns
t
WDD
—
70
—
80
—
90
ns
t
DDD
—
45
—
55
—
70
ns
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary
over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0
°
C to +70
°
C temperature range .
6. “X” in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
(1)
2720 tbl 10
2.
CE
L =
CE
R =
V
IL.
OE
"B"
= V
IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2720 drw 10
R/
W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
AW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7134LA45L48 | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA45L48B | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA45P | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134SA45C | 30V P-Channel PowerTrench MOSFET |
| IDT7134SA45F | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
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