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參數(shù)資料
| 型號(hào)： | IDT7134LA55F |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 150V N-Channel UltraFET Trench MOSFET |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 55 ns, CQFP48 |
| 封裝： | CERAMIC, FP-48 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | IDT7134LA55F |
6.04
7
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(6)
(CONT'D)
7134X45
Min.
7134X55
Min.
7134X70
Min.
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
Parameter
Max.
Max.
Max.
Unit
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write RecoveryTime
Data Valid to End-of-Write
Output High-Z Time
(1, 2)
Data Hold Time
(3)
Write Enabled to Output in High-Z
(1, 2)
45
40
40
0
40
0
20
—
—
—
—
—
—
—
55
50
50
0
50
0
25
—
—
—
—
—
—
—
70
60
60
0
60
0
30
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
t
HZ
—
20
—
25
—
30
ns
t
DH
3
—
3
—
3
—
ns
t
WZ
—
20
—
25
—
30
ns
t
OW
Output Active from End-of-Write
(1, 2, 3)
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4)
3
—
3
—
3
—
ns
t
WDD
—
70
—
80
—
90
ns
t
DDD
—
45
—
55
—
70
ns
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary
over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0
°
C to +70
°
C temperature range .
6. “X” in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
(1)
2720 tbl 10
2.
CE
L =
CE
R =
V
IL.
OE
"B"
= V
IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2720 drw 10
R/
W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
AW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7134LA55FB | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA55J | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA55L48 | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA55L48B | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA55P | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT7134LA55J | 功能描述:IC SRAM 32KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA55J8 | 功能描述:IC SRAM 32KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7134LA55L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 55NS 48LCC |
| IDT7134LA55P | 功能描述:IC SRAM 32KBIT 55NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA70CB | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS SB48 |
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