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參數(shù)資料
| 型號： | IDT7134LA55L48B |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 55 ns, CQCC48 |
| 封裝： | LCC-48 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 110K |
| 代理商： | IDT7134LA55L48B |
6.04
5
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(4)
(CONT'D)
7134X45
7134X55
7134X70
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
AOE
t
OH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
45
—
—
—
0
—
45
45
25
—
55
—
—
—
0
—
55
55
30
—
70
—
—
—
0
—
70
70
40
—
ns
ns
ns
ns
ns
t
LZ
5
—
5
—
5
—
ns
t
HZ
—
20
—
25
—
30
ns
t
PU
0
—
0
—
0
—
ns
t
PD
—
45
—
50
—
50
ns
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. (Commercial only) 0
°
C to +70
°
C temperature range only.
4. “X” in part number indicates power rating (SA or LA).
2720 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1, 2, 3)
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(4)
7134X20
(3)
7134X25
7134X35
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
AOE
t
OH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
20
—
—
—
0
—
20
20
15
—
25
—
—
—
0
—
25
25
15
—
35
—
—
—
0
—
35
35
20
—
ns
ns
ns
ns
ns
t
LZ
0
—
0
—
0
—
ns
t
HZ
—
15
—
15
—
20
ns
t
PU
0
—
0
—
0
—
ns
t
PD
—
20
—
25
—
35
ns
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first,
OE
or
CE
.
3. R/
W
= V
IH
.
ADDRESS
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
t
OH
t
OH
t
AA
t
RC
2720 drw 08
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7134LA55P | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA55PB | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA70C | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA70CB | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| IDT7134LA70F | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7134LA55P | 功能描述:IC SRAM 32KBIT 55NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA70CB | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS SB48 |
| IDT7134LA70J | 功能描述:IC SRAM 32KBIT 70NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7134LA70J8 | 功能描述:IC SRAM 32KBIT 70NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7134LA70L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS 48LCC |
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