參數(shù)資料
型號(hào)： IDT7134SA45P
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
中文描述： 4K X 8 DUAL-PORT SRAM, 45 ns, PDIP48
封裝： PLASTIC, DIP-48
文件頁(yè)數(shù)： 2/9頁(yè)
文件大?。?/td> 110K
代理商： IDT7134SA45P
6.04
2
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of actual part-marking.
A
10R
OE
2720 drw 02
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
9R
A
8R
A
7R
A
6R
A
4R
A
5R
A
3R
A
2R
A
1R
A
0R
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
IDT7134
P48–1
&
C48–2
DIP
TOP
VIEW
(3)
CE
L
R/
W
L
A
11L
A
10L
OE
L
V
CC
CE
R
R
A
11R
R/
W
R
2720 drw 04
IDT7134
L48-1
&
F48-1
LCC/Flatpack
TOP VIEW
(3)
INDEX
6 5
4 3
2
1
48 47 46 45 44 43
19 20 21 22 23
25 26 27 28 29 30
24
G
I
3
I
4
I
5
L
I
6
I
0
I
1
I
2
I
3
I
4
I
5
I
7
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
42
41
40
39
38
37
36
35
34
33
32
31
7
8
9
10
11
12
13
14
15
16
17
18
A
0
V
C
O
L
R
W
L
C
R
R
W
R
C
L
O
R
A
1
A
1
A
1
A
1
2720 drw 03
IDT7134
J52-1
PLCC
TOP VIEW (3)
INDEX
N
G
I
4
I
5
I
6
I
7
I
0
I
1
I
2
I
3
I
4
I
5
I
6
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
47
48
49
50
51
52
1
2
3
4
5
6
7
33
32
31
30
29
28
27
26
25
24
23
22
21
A
0
V
C
O
L
R
W
L
C
R
R
W
R
C
L
A
1
A
1
A
1
A
1
N
N
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com’l.
Mil.
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to Ground
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
–0.5 to +7.0
–0.5 to +7.0
V
0 to +70
–55 to +125
°
C
–55 to +125
–65 to +135
°
C
–55 to +125
–65 to +150
°
C
P
T
(3)
Power Dissipation
1.5
1.5
W
I
OUT
DC Output Current
50
50
mA
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25%of the cycle time or
10 ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+0.5V.
CAPACITANCE
(1)
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
V
IN
= 3dv
V
OUT
= 3dv
11
11
pF
pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V and from 3V to 0V.
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