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參數(shù)資料
| 型號： | IDT7134SA55P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 55 ns, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 110K |
| 代理商： | IDT7134SA55P |
6.04
6
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(1, 3)
2720 drw 09
CE
DATA
OUT
VALID DATA
(4)
t
PD
t
AOE
(4)
t
ACE
OE
t
HZ
(2)
t
LZ
(1)
t
LZ
(1)
t
PU
50%
50%
I
CC
I
SB
CURRENT
t
HZ
(2)
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first,
OE
or
CE
.
3. R/
W
= V
IH
.
4. Start of valid data depends on which timing becomes effective , t
AOE
, t
ACE
or t
AA
5. t
AA
for RAM Address Access and t
SAA
for Semaphore Address Access.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(6)
7134X20
(5)
Min.
7134X25
Min.
7134X35
Min.
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
Parameter
Max.
Max.
Max.
Unit
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write RecoveryTime
Data Valid to End-of-Write
Output High-Z Time
(1, 2)
Data Hold Time
(3)
Write Enabled to Output in High-Z
(1, 2)
20
15
15
0
15
0
15
—
—
—
—
—
—
—
25
20
20
0
20
0
15
—
—
—
—
—
—
—
35
30
30
0
25
0
20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
t
HZ
—
15
—
15
—
20
ns
t
DH
0
—
0
—
3
—
ns
t
WZ
—
15
—
15
20
ns
t
OW
Output Active from End-of-Write
(1, 2, 3)
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4, 7)
3
—
3
—
3
—
ns
t
WDD
—
40
—
50
—
60
ns
t
DDD
—
30
—
30
—
35
ns
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary
over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0
°
C to +70
°
C temperature range .
6. “X” in part number indicates power rating (SA or LA).
7. t
DDD
= 35ns for military temperature range.
2720 tbl 10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7134SA70CB | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS SB48 |
| IDT7134SA70J | 功能描述:IC SRAM 32KBIT 70NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7134SA70J8 | 功能描述:IC SRAM 32KBIT 70NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7134SA70L48B | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS 48LCC |
| IDT7134SA70P | 功能描述:IC SRAM 32KBIT 70NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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