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參數(shù)資料
| 型號： | IDT7140LA25TFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 1K X 8 DUAL-PORT SRAM, 25 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | IDT7140LA25TFB |
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.01
6
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(3)
7130X20
(2)
7130X25
(5)
7130X35
7140X35
7130X55
7140X55
7130X100
7140X100
7140X25
(5)
Min. Max. Min.
Symbol
Parameter
Min. Max.
Max. Min. Max. Min.
Max. Unit
Read Cycle
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0
°
C to +70
°
C temperature range. PLCC and TQFP package.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time
(1,4)
Output High-Z Time
(1,4)
Chip Enable to Power Up Time
(4)
Chip Disable to Power Down Time
(4)
20
—
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
0
—
0
—
—
25
25
12
—
—
10
—
25
35
—
—
—
3
0
—
0
—
—
35
35
20
—
—
15
—
35
55
—
—
—
3
5
—
0
—
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
0
—
—
100
100
40
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
0
—
0
—
2689 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2689 drw 08
t
BDD
(2,3)
BUSY
OUT
NOTES:
1.
R/
W
= V
IH
,
CE
= V
IL
, and is
OE
= V
IL
. Address is valid prior to the coincidental with
CE
transition Low.
2.
t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same the
address location. For simultaneous read operations,
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
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| IDT7140LA35C | 功能描述:IC SRAM 8KBIT 35NS 48DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7140LA35CB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS SB48 |
| IDT7140LA35FB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS 48FPACK |
| IDT7140LA35J | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT7140LA35J8 | 功能描述:IC SRAM 8KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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