參數(shù)資料
型號: IDT7140LA35TF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
中文描述: 1K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封裝: STQFP-64
文件頁數(shù): 11/14頁
文件大小: 218K
代理商: IDT7140LA35TF
6.01
11
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(2)
8M824S25
7130X55
7140X55
Min.
8M824S308M824S35
7130X100
7140X100
Min.
Max.
7130X20
(1)
7130X25
(3)
7140X25
(3)
Min.
7130X35
7140X35
Min. Max.
Symbol
Interrupt Timing
t
AS
t
WR
t
INS
t
INR
Parameter
Min.
Max.
Max.
Max.
Unit
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
20
20
0
0
25
25
0
0
25
25
0
0
45
45
0
0
60
60
ns
ns
ns
ns
2689 tbl 12
NOTES:
1.
2.
3.
0
°
C to +70
°
C temperature range only, PLCC and TQFP packages.
“X” in part numbers indicates power rating (SA or LA).
Not available in DIP packages .
INT
SET:
TIMING WAVEFORM OF INTERRUPT MODE
INT
CLEAR:
NOTES:
.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
4. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
t
INS
ADDR
'A'
INT
'B'
INTERRUPT ADDRESS
t
WC
t
AS
R/
W
'A'
t
WR
2689 drw 16
(3)
(3)
(2)
(4)
t
RC
INTERRUPT CLEAR ADDRESS
ADDR
'B'
OE
'B'
t
INR
INT
'B'
2689 drw 17
t
AS
(3)
(3)
相關(guān)PDF資料
PDF描述
IDT7140LA55C HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
IDT7140LA55CB HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
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