參數(shù)資料
型號(hào): IDT7140SA35TFB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
中文描述: 1K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封裝: STQFP-64
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 218K
代理商: IDT7140SA35TFB
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.01
10
TIMING WAVEFORM OF WRITE WITH
BUSY
(3)
BUSY
'B'
2689 drw 13
R/
W
'A'
t
WP
t
WH
t
WB
R/
W
'B'
(2)
(1)
NOTES:
1.
t
WH
must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING
(1)
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
(1)
t
RC
OR
t
WC
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be
asserted (7130 only).
t
APS
ADDR
'A'
AND
'B'
ADDRESSES MATCH
t
BAC
t
BDC
CE
'B'
CE
'A'
BUSY
'A'
2689 drw 14
(2)
BUSY
'B'
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
ADDR
'A'
ADDR
'B'
2689 drw 15
(2)
t
BAA
t
BDA
相關(guān)PDF資料
PDF描述
IDT7130LA35TFB HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
IDT7140LA35TFB HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
IDT7130SA55TFB HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
IDT7130SA100C HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
IDT7130SA100CB HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
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