參數(shù)資料
型號: IDT71421LA35J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
中文描述: 2K X 8 DUAL-PORT SRAM, 35 ns, PQCC52
封裝: 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
文件頁數(shù): 8/16頁
文件大小: 255K
代理商: IDT71421LA35J
8
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side
(1)
Timing Waveform of Read Cycle No. 2, Either Side
(1)
NOTES:
1.
2.
R/
W
= V
IH,
CE
= V
IL,
and is
OE
= V
IL.
Address is valid prior to the coincidental with
CE
transition LOW.
t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations,
BUSY
has
no relationship to valid output data.
Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
Timing depends on which signal is asserted last,
OE
or
CE
.
Timing depends on which signal is de-asserted first,
OE
or
CE
.
3.
4.
5.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2692 drw 07
t
BDDH
(2,3)
BUSY
OUT
CE
t
HZ
(5)
t
LZ
(4)
t
PD
(3)
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2692 drw 08
t
LZ
(4)
t
HZ
(5)
t
ACE
t
AOE
(3)
相關(guān)PDF資料
PDF描述
IDT71421LA35JI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA35PF HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA35PFI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA35TF HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT71421LA35TFI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
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