參數(shù)資料
型號: IDT7142LA55JB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
中文描述: 2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52
封裝: 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
文件頁數(shù): 12/16頁
文件大?。?/td> 255K
代理商: IDT7142LA55JB
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,3,4)
Timing Waveform of Write with
BUSY
(4)
NOTES:
1.
2.
3.
4.
t
WH
must be met for both
BUSY
Input (IDT7142, slave) or Output (IDT7132, master).
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
t
WB
applies only to the slave version (IDT7142).
All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
BUSY
"B"
2692 drw 12
R/
W
"A"
t
WP
t
WH
(1)
t
WB
R/
W
"B"
(2)
(3)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/
W
"A"
BUSY
"B"
t
APS
(1)
2692 drw 11
t
BAA
NOTES:
1.
2.
3.
4.
To ensure that the earlier of the two ports wins.
t
APS
is ignored for Slave (IDT7142).
CE
L
=
CE
R
= V
IL
OE
= V
IL
for the reading port.
All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
相關PDF資料
PDF描述
IDT7142LA55JI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7142LA55L48I HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7142SA100L48I HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7142SA100PI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
IDT7142SA20CI HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
相關代理商/技術參數(shù)
參數(shù)描述
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