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| 型號(hào)： | IDT7142SA20L48B |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速2K × 8雙端口靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | IDT7142SA20L48B |
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.02
6
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(5)
7132X20
(2)
7132X25
(6)
7142X25
(6)
Min. Max.
7132X35
7142X35
Min.
7132X55
7142X55
Min.
7132X100
7142X100
Min.
Symbol
Write Cycle
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Parameter
Min.
Max.
Max.
Max.
Max.
Unit
Write Cycle Time
(3)
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
(4)
Write Recovery Time
Data Valid to End of Write
Output High Z Time
(1)
Data Hold Time
Write Enabled to Output in High Z
(1)
Output Active From End of Write
(1)
20
15
15
0
15
0
10
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
25
20
20
0
15
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
25
0
15
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
55
40
40
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
25
—
30
—
100
90
90
0
55
0
40
—
0
—
0
—
—
—
—
—
—
—
40
—
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(3)
CAPACITANCE
(1)
(T
A
= +25
°
C,f = 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
Conditions
(2)
V
IN
= 3dV
V
IN
= 3dV
Max.
11
11
Unit
pF
pF
2692 tbl 10
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2692 drw 08
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
t
AOE
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is deaserted first,
OE
or
CE
.
3. R/
W
= V
IH
, and the address is valid prior to or coincidental with
CE
transition Low.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0
°
C to +70
°
C temperature range only, PLCC package only.
3. For Master/Slave combination, t
WC
= t
BAA
+ t
WP
, since R/
W
=
V
IL
must occur after t
BAA
.
4. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
2692 tbl 09
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|---|---|
| IDT7142SA25J | 功能描述:IC SRAM 16KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7142SA25J8 | 功能描述:IC SRAM 16KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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