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參數(shù)資料
| 型號(hào)： | IDT7142SA20PB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速2K × 8雙端口靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | IDT7142SA20PB |
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.02
8
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(7)
8
M824S258M824S30
7132158M824S4
7132X100
7142X100
7132X20
(1)
7132X25
(8)
7142X25
(8)
Min. Max.
7132X35
7142X35
Min. Max.
7132X55
7142X55
Min. Max. Min. Max.
Symbol
Busy Timing (For Master lDT7130 Only)
t
BAA
BUSY
Access Time from Address
t
BDA
BUSY
Disable Time from Address
t
BAC
BUSY
Access Time from Chip Enable
t
BDC
BUSY
Disable Time from Chip Enable
t
WDD
Write Pulse to Data Delay
(2)
t
WH
Write Hold After
BUSY
(6)
t
DDD
Write Data Valid to Read Data Delay
(2)
t
APS
Arbitration Priority Set-up Time
(3)
t
BDD
BUSY
Disable to Valid Data
(4)
Busy Timing (For Slave IDT7140 Only)
e
t
WB
Write to
BUSY
Input
(5)
t
WH
Write Hold After
BUSY
(6)
t
WDD
Write Pulse to Data Delay
(2)
t
DDD
Write Data Valid to Read Data Delay
(2)
NOTES:
1. Com'l Only, 0
°
C to +70
°
C temperature range. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and
BUSY
."
3. To ensure that the earlier of the two ports wins.
4. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (S or L).
8. Not available in DIP package
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
Parameter
Min. Max.
Unit
—
—
—
—
—
12
—
5
—
5
0
12
—
—
20
20
20
20
50
—
35
—
25
—
—
—
40
30
—
—
—
—
—
15
—
5
—
5
0
15
—
—
20
20
20
20
50
—
35
—
35
—
—
—
50
35
—
—
—
—
—
20
—
5
—
5
0
20
—
—
20
20
20
20
60
—
35
—
35
—
—
—
60
35
—
—
—
—
—
20
—
5
—
5
0
20
—
—
30
30
30
30
80
—
55
—
50
—
—
—
80
55
—
—
—
—
—
20
—
5
—
5
0
20
—
—
50
50
50
50
120
—
100
—
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
120
100
ns
ns
ns
ns
2689 tbl 11
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
’B’
DATA
OUT’B’
DATA
IN’A’
ADDR
’A’
MATCH
VALID
MATCH
VALID
R/
W
’A’
BUSY
’B’
t
APS
2692 drw 11
(1)
NOTES:
1. To ensure that the earlier of the two ports wins.
t
APS
is ignored for Slave (IDT7142).
2.
CE
L
=
CE
R
= V
IL.
3.
OE
= V
IL
for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port 'B' is opposite from port 'A'.
BUSY
(1,2,3)
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| IDT7142SA25J | 功能描述:IC SRAM 16KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
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| IDT7142SA35CB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 35NS SB48 |
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