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參數(shù)資料
| 型號： | IDT7143LA70GB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 70 ns, CPGA68 |
| 封裝： | CERAMIC, PGA-68 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IDT7143LA70GB |
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
NOTES:
1.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
.
3.
t
WR
is measured fromthe earlier of
CE
or R/
W
going HIGH to the end of the write cycle.
4.
During this period, the I/O pins are in the output state, and input signals must not be applied.
5.
If the
CE
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6.
Timng depends on which enable signal (
CE
or R/
W
) is asserted last.
7.
Timng depends on which enable signal is de-asserted first,
CE
or
OE
.
8. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP
.
9. R/
W
for either upper or lower byte.
R/
W
or
CE
must be HIGH during all address transitions.
82#
CE
-$!
(!
$8582#,=
W
-$!
(>!
CE
2746 drw 09
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/
W
t
WP
t
DH
DATA
OUT
t
WZ
(7)
(4)
(2)
t
OW
OE
(9)
t
LZ
(7)
t
HZ
(6)
(3)
(4)
(7)
t
HZ
CE
2746 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/
W
t
EW
t
DH
(9)
(6)
(2)
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