參數(shù)資料
型號： IDT7143SA55GI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
中文描述： 2K X 16 DUAL-PORT SRAM, 55 ns, CPGA68
封裝： CERAMIC, PGA-68
文件頁數(shù)： 15/16頁
文件大?。?/td> 140K
代理商： IDT7143SA55GI
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
$*$4@A;,-=8
B!
$*$4@@C%--
%4
BUSY
NOTES:
1.
Pins
BUSY
L
and
BUSY
R
are both outputs on the IDT7133 (MASTER). Both are
inputs on the IDT7143 (SLAVE). On Slaves the
BUSY
input internally inhibits
writes.
"L" if the inputs to the opposite port were stable prior to the address and enable
inputs of this port.
“
H
”
if the inputs to the opposite port became stable after the
address and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= V
IL
will result
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on
the pin.
2.
3.
NOTES:
1.
2.
3.
4.
A
0L
- A
10L
≠
A
0R
- A
10R
If
BUSY
= LOW, data is not written.
If
BUSY
= LOW, data may not be valid, see t
WDD
and t
DDD
timng.
"H" = HIGH, "L" = LOW, "X" = Don
’
t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte
LEFT OR RIGHT PORT
(1)
Function
R/
W
LB
R/
W
UB
CE
OE
I/O
0-7
I/O
8-15
X
X
H
X
Z
Z
Port Disabled and in Power Down Mode, I
SB2
, I
SB4
X
X
H
X
Z
Z
CE
R
= CE
L
= V
IH
, Power Down Mode, I
SB1
or I
SB3
L
L
L
X
DATA
IN
DATA
IN
Data on Lower Byte and Upper Byte Written into Memory
(2)
L
H
L
L
DATA
IN
DATA
OUT
Data on Lower Byte Written into Memory
(2)
, Data in Memory Output on
Upper Byte
(3)
H
L
L
L
DATA
OUT
DATA
IN
Data in Memory Output on Lower Byte
(3)
, Data on Upper Byte Written into
Memory
(2)
L
H
L
H
DATA
IN
Z
Data on Lower Byte Written into Memory
(2)
H
L
L
H
Z
DATA
IN
Data on Upper Byte Written into Memory
(2)
H
H
L
L
DATA
OUT
DATA
OUT
Data in Memory Output on Lower Byte and Upper Byte
H
H
L
H
Z
Z
High Impedance Outputs
2746 tbl 13
Inputs
Outputs
Function
CE
L
CE
R
A
0L
-A
10L
A
0R
-A
10R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
2746 tbl 14
相關(guān)PDF資料
PDF描述
IDT7143SA55J P-Channel 2.5V Specified MOSFET
IDT7143SA55JI HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
IDT7143SA55PF HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
IDT7143SA55PFB HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
IDT7143SA55PFI HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT7143SA55J 功能描述:IC SRAM 32KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI
IDT7143SA55J8 功能描述:IC SRAM 32KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI
IDT7143SA55PF 功能描述:IC SRAM 32KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI
IDT7143SA55PF8 功能描述:IC SRAM 32KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)
IDT7143SA70GB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 70NS 68PGA
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