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參數(shù)資料
| 型號(hào)： | IDT7164L25DB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS STATIC RAM 64K (8K x 8-BIT) |
| 中文描述： | 8K X 8 STANDARD SRAM, 25 ns, CDIP28 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 104K |
| 代理商： | IDT7164L25DB |
6.1
8
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 6)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2)
NOTES:
1.
WE
,
CS
1
or CS
2
must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW
WE
, a LOW
CS
1
and a HIGH CS
2
.
3. t
WR1, 2
is measured from the earlier of
CS
1
or
WE
going HIGH or CS
2
going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
1
LOW transition or CS
2
HIGH transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6.
OE
is continuously HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+t
DW
) to allow the
I/O drivers to turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not
apply and the minimum write pulse width is as short as the specified t
WP
.
7. Transition is measured
±
200mV from steady state.
ADDRESS
t
WC
t
WHZ(7)
2967 drw 08
CS
1
DATA
OUT
CS
2
t
AS
t
AW
t
WR1(3)
WE
t
WP
t
OW(7)
DATA
IN
t
DH1, 2
t
DW
DATA VALID
(4)
(6)
2967 drw 09
ADDRESS
CS
1
CS
2
t
WC
t
AS
WE
t
CW
t
WR2(3)
t
AW
DATA
IN
t
DH1,2
t
DW
DATA VALID
t
WR1(3)
(5)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7164L25P | CMOS STATIC RAM 64K (8K x 8-BIT) |
| IDT7164L25PB | CMOS STATIC RAM 64K (8K x 8-BIT) |
| IDT7164L25TD | CMOS STATIC RAM 64K (8K x 8-BIT) |
| IDT7164L25TDB | Dual UART With 64-Byte FIFO 32-QFN 0 to 70 |
| IDT7164L25TP | Replaced by TL16C754B : Quad UART with 64-Byte Fifos, Auto Flow Control, Low-Power Modes 68-PLCC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7164L25TDB | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 25NS 28CDIP |
| IDT7164L25YG | 功能描述:IC SRAM 64KBIT 25NS 28SOJ RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán) |
| IDT7164L25YG8 | 功能描述:IC SRAM 64KBIT 25NS 28SOJ RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán) |
| IDT7164L25YGI | 功能描述:IC SRAM 64KBIT 25NS 28SOJ RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán) |
| IDT7164L25YGI8 | 功能描述:IC SRAM 64KBIT 25NS 28SOJ RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán) |
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