參數(shù)資料
型號(hào): IDT71P74604S300BQ
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 18Mb Pipelined QDR II SRAM Burst of 4
中文描述: 512K X 36 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 9/22頁(yè)
文件大?。?/td> 592K
代理商: IDT71P74604S300BQ
6.42
9
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Absolute Maximum Ratings
(1) (2)
Capacitance
(T
A
= +25°C, f = 1.0MHz)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximumrating conditions for extended periods may affect
reliability.
2. V
DDQ
must not exceed V
DD
during normal operation.
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
DD
= 1.8V
V
DDQ
= 1.5V
5
pF
C
CLK
Clock Input Capacitance
6
pF
C
O
Output Capacitance
7
pF
6111 tbl 06
Symbol
Rating
Value
Unit
V
TERM
Supply Voltage on V
DD
with
Respect to GND
–0.5 to +2.9
V
V
TERM
Supply Voltage on V
DDQ
with
Respect to GND
–0.5 to V
DD
+0.3
V
V
TERM
Voltage on Input termnals wth
respect to GND
–0.5 to V
DD
+0.3
V
V
TERM
Voltage on Output and I/O
terminals wth respect to GND.
–0.5 to V
DDQ
+0.3
V
T
BIAS
Temperature Under Bias
–55 to +125
°C
T
STG
Storage Temperature
–65 to +150
°C
I
OUT
Continuous Current into Outputs
+ 20
mA
6111 tbl 05
Recommended DC Operating and
Temperture Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Power Supply
Voltage
1.7
1.8
1.9
V
V
DDQ
I/O Supply Voltage
1.4
1.5
1.9
V
V
SS
Ground
0
0
0
V
V
REF
Input Reference
Voltage
0.68
V
DDQ
/2
0.95
V
T
A
Ambient
Temperature
(1)
0
25
+70
o
c
6111 tbl 04
NOTES:
1)
All byte write
(
BW
x)
and nibble write
(
NW
x)
signals are sampled
on the
rising edge of K and again on
K
. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding
BW
x or
NW
x is held low. The rising edge of K will sample the first and third bytes/
nibbles of the four word burst and the rising edge of
K
will sample the second
and fourth bytes/nibbles of the four word burst.
2) The availability of the
BW
x or
NW
x on designated devices is described in
the pin description table.
3) The QDRII Burst of four SRAMhas data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data in response to the read request.
Signal
BW
0
BW
1
BW
2
BW
3
NW
0
NW
1
Write Byte 0
L
X
X
X
X
X
Write Byte 1
X
L
X
X
X
X
Write Byte 2
X
X
L
X
X
X
Write Byte 3
X
X
X
L
X
X
Write Nibble 0
X
X
X
X
L
X
Write Nibble 1
X
X
X
X
X
L
6111 tbl 09
Write Descriptions
(1,2)
NOTE:
1. During production testing, the case temperarure equals the ambient
temperature.
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