參數(shù)資料
型號: IDT71P74804S200BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 18Mb Pipelined QDR II SRAM Burst of 4
中文描述: 1M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù): 11/22頁
文件大小: 592K
代理商: IDT71P74804S200BQ
6.42
11
IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
Input Leakage Current
I
IL
V
DD
= Max V
IN
= V
SS
to V
DDQ
-10
+10
μ
A
Output Leakage Current
I
OL
Output Disabled
-10
+10
μ
A
Operating Current
(x36,x18,x9,x8): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Min
333MH
Z
-
TBD
mA
1
300MH
Z
-
TBD
250MH
Z
-
TBD
300MHz
-
TBD
167MHz
-
TBD
Standby Current: NOP
I
SB1
Device Deselected (in NOP state)
I
OUT
= 0mA (outputs open),
f=Max,
All Inputs <0.2V or > VDD -0.2V
333MH
Z
-
TBD
mA
2
300MH
Z
-
TBD
250MH
Z
-
TBD
200MHz
-
TBD
167MHz
-
TBD
Output High Voltage
V
OH1
RQ = 250
,
I
OH
= -15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
3,7
Output Low Voltage
V
OL1
RQ = 250
,
I
OL
= 15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
4,7
Output High Voltage
V
OH2
I
OH
= -0.1mA
V
DDQ
-0.2
V
DDQ
V
5
Output Low Voltage
V
OL2
I
OL
= 0.1mA
V
SS
0.2
V
6
6111 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. I
OH
= -(V
DDQ
/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This
parameter is tested at RQ = 250
,
which gives a nomnal 50
output impedance.
4. Outputs are impedance-controlled. I
OL
= (V
DDQ
/2)/(RQ/5) and is guaranteed by device characterization for 175
< RQ < 350
.
This
parameter is tested at RQ = 250
,
which gives a nomnal 50
output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the V
DDQ
rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to V
ss
, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
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