參數(shù)資料
型號: IDT71T016SA12BFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
中文描述: 64K X 16 STANDARD SRAM, 12 ns, PBGA48
封裝: 7 X 7 MM, PLASTIC, FBGA-48
文件頁數(shù): 6/9頁
文件大?。?/td> 113K
代理商: IDT71T016SA12BFI
6.42
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the mnimumwrite pulse is as short as the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS
,
BHE
, or
BLE
transition LOW; otherwise t
AA
is the limting parameter.
3. Transition is measured ±200mV fromsteady state.
ADDRESS
OE
CS
DATA
OUT
5326 drw 07
(3)
(3)
(3)
DATA
VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
BHE
,
BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
ADDRESS
CS
DATA
IN
5326 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID
DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
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IDT71T016SA12PH 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
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