參數(shù)資料
型號: IDT71V124SA15PHI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: ROHS COMPLIANT, TSOP2-32
文件頁數(shù): 1/8頁
文件大小: 81K
代理商: IDT71V124SA15PHI
1
2003- Integrated Device Technology, Inc.
NOVEMBER 2003
DSC-3873/07
Features
N
128K x 8 advanced high-speed CMOS static RAM
N
JEDEC revolutionary pinout (center power/GND) for
reduced noise
N
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
N
One Chip Select plus one Output Enable pin
N
Inputs and outputs are LVTTL-compatible
N
Single 3.3V supply
N
Low power consumption via chip deselect
N
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Functional Block Diagram
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAMorganized
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves systemperformance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is froma single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
16
3873 drw 01
8
8
I/O
0
- I/O
7
8
CONTROL
LOGIC
WE
OE
CS
.
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA
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相關代理商/技術參數(shù)
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