• 參數(shù)資料
    型號: IDT71V2556SA133BG
    廠商: INTEGRATED DEVICE TECHNOLOGY INC
    元件分類: DRAM
    英文描述: 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
    中文描述: 128K X 36 ZBT SRAM, 4.2 ns, PBGA119
    封裝: 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
    文件頁數(shù): 22/28頁
    文件大?。?/td> 1019K
    代理商: IDT71V2556SA133BG
    6.42
    22
    IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs
    with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
    JTAG Interface Specification (SA Version only)
    TCK
    Device Inputs
    (1)
    /
    TDI/TMS
    Device Outputs
    (2)
    /
    TDO
    TRST
    (
    3)
    t
    JCD
    t
    JDC
    t
    JRST
    t
    JS
    t
    JH
    t
    JCYC
    t
    JRSR
    t
    JF
    t
    JCL
    t
    JR
    t
    JCH
    M4875 drw 01
    x
    Symbol
    Parameter
    Mn.
    Max.
    Units
    t
    J CYC
    JTAG Clock Input Period
    100
    ____
    ns
    t
    JCH
    JTAG Clock HIGH
    40
    ____
    ns
    t
    JCL
    JTAG Clock Low
    40
    ____
    ns
    t
    JR
    JTAG Clock Rise Time
    ____
    5
    (1)
    ns
    t
    JF
    JTAG Clock Fall Time
    ____
    5
    (1)
    ns
    t
    JRST
    JTAG Reset
    50
    ____
    ns
    t
    J RSR
    JTAG Reset Recovery
    50
    ____
    ns
    t
    JCD
    JTAG Data Output
    ____
    20
    ns
    t
    JDC
    JTAG Data Output Hold
    0
    ____
    ns
    t
    JS
    JTAG Setup
    25
    ____
    ns
    t
    JH
    JTAG Hold
    25
    ____
    ns
    I4875 tbl 01
    Register Name
    Bit Size
    Instruction (IR)
    4
    Bypass (BYR)
    1
    JTAG Identification (JIDR)
    32
    Boundary Scan (BSR)
    Note (1)
    I4875 tbl 03
    NOTES:
    1. Device inputs = All device inputs except TDI, TMS and
    TRST
    .
    2. Device outputs = All device outputs except TDO.
    3. During power up,
    TRST
    could be driven low or not be used since the JTAG circuit resets automatically.
    TRST
    is an optional JTAG reset.
    NOTE:
    1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
    by contacting your local IDT sales representative.
    JTAG AC Electrical
    Characteristics
    (1,2,3,4)
    Scan Register Sizes
    NOTES:
    1. Guaranteed by design.
    2. AC Test Load (Fig. 1) on external output signals.
    3. Refer to AC Test Conditions stated earlier in this document.
    4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
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