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參數(shù)資料
| 型號： | IDT71V2558SA100PFI |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| 中文描述： | 128K的× 36，256 × 18 3.3同步ZBT SRAM的2.5VI / O的脈沖計(jì)數(shù)器輸出流水線 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | IDT71V2558SA100PFI |
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OCTOBER 2004
DSC-4875/08
1
2004 Integrated Device Technology, Inc.
Pin Description Summary
A
0
-A
17
Description
The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to elimnate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAMduring one clock
Features
N
128K x 36, 256K x 18 memory configurations
N
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
N
ZBT
TM
Feature - No dead cycles between write and read
cycles
N
Internally synchronized output buffer enable eliminates the
need to control
OE
N
Single R/
W
(READ/WRITE) control pin
N
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
N
4-word burst capability (interleaved or linear)
N
Individual byte write (
BW
1
-
BW
4
) control (May tie active)
N
Three chip enables for simple depth expansion
N
3.3V power supply (±5%), 2.5V I/O Supply (V
DDQ)
N
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
N
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
Static
V
SS
Ground
Supply
Static
IDT71V2556S
IDT71V2558S
IDT71V2556SA
IDT71V2558SA
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (
CEN
) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (
CEN
) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/
LD
is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/
LD
signal is used to load a new external address
(ADV/
LD
= LOW) or increment the internal burst counter (ADV/
LD
=
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V2558SA133BG | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| IDT71V2558SA133BGI | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| IDT71V2558SA133BQ | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| IDT71V2558SA133BQI | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
| IDT71V2558SA133PF | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V2559S75BG | 功能描述:IC SRAM 4MBIT 75NS 119BGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
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