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  • 參數(shù)資料
    型號: IDT71V2558SA133BQI
    廠商: INTEGRATED DEVICE TECHNOLOGY INC
    元件分類: DRAM
    英文描述: 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
    中文描述: 256K X 18 ZBT SRAM, 4.2 ns, PBGA165
    封裝: 13 X 15 MM, FBGA-165
    文件頁數(shù): 11/28頁
    文件大?。?/td> 1019K
    代理商: IDT71V2558SA133BQI
    6.42
    IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs
    with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
    Device Operation - Showint Mixed Load, Burst,
    Deselect and NOOP Cycles
    (2)
    CEN
    BW
    x
    11
    NOTES:
    1. H = High; L = Low; X = Dont Care; Z = High Impedance.
    2.
    CE
    = L is defined as
    CE
    1
    = L,
    CE
    2
    = L and CE
    2
    = H.
    CE
    = H is defined as
    CE
    1
    = H,
    CE
    2
    = H or CE
    2
    = L.
    Read Operation
    (1)
    NOTES:
    1.
    CE
    = L is defined as
    CE
    1
    = L,
    CE
    2
    = L and CE
    2
    = H.
    CE
    = H is defined as
    CE
    1
    = H,
    CE
    2
    = H or CE
    2
    = L.
    2. H = High; L = Low; X = Dont Care; Z = High Impedance.
    Cycle
    Address
    R/
    W
    ADV/
    LD
    CE
    (1)
    OE
    I/O
    Comments
    n
    A
    0
    H
    L
    L
    L
    X
    X
    X
    Load read
    n+1
    X
    X
    H
    X
    L
    X
    X
    X
    Burst read
    n+2
    A
    1
    H
    L
    L
    L
    X
    L
    Q
    0
    Load read
    n+3
    X
    X
    L
    H
    L
    X
    L
    Q
    0+1
    Deselect or STOP
    n+4
    X
    X
    H
    X
    L
    X
    L
    Q
    1
    NOOP
    n+5
    A
    2
    H
    L
    L
    L
    X
    X
    Z
    Load read
    n+6
    X
    X
    H
    X
    L
    X
    X
    Z
    Burst read
    n+7
    X
    X
    L
    H
    L
    X
    L
    Q
    2
    Deselect or STOP
    n+8
    A
    3
    L
    L
    L
    L
    L
    L
    Q
    2+1
    Load write
    n+9
    X
    X
    H
    X
    L
    L
    X
    Z
    Burst write
    n+10
    A
    4
    L
    L
    L
    L
    L
    X
    D
    3
    Load write
    n+11
    X
    X
    L
    H
    L
    X
    X
    D
    3+1
    Deselect or STOP
    n+12
    X
    X
    H
    X
    L
    X
    X
    D
    4
    NOOP
    n+13
    A
    5
    L
    L
    L
    L
    L
    X
    Z
    Load write
    n+14
    A
    6
    H
    L
    L
    L
    X
    X
    Z
    Load read
    n+15
    A
    7
    L
    L
    L
    L
    L
    X
    D
    5
    Load write
    n+16
    X
    X
    H
    X
    L
    L
    L
    Q
    6
    Burst write
    n+17
    A
    8
    H
    L
    L
    L
    X
    X
    D
    7
    Load read
    n+18
    X
    X
    H
    X
    L
    X
    X
    D
    7+1
    Burst read
    n+19
    A
    9
    L
    L
    L
    L
    L
    L
    Q
    8
    Load write
    4875 tbl 12
    Cycle
    Address
    R/
    W
    ADV/
    LD
    CE
    (2)
    CEN
    BW
    x
    OE
    I/O
    Comments
    n
    A
    0
    H
    L
    L
    L
    X
    X
    X
    Address and Control meet setup
    n+1
    X
    X
    X
    X
    L
    X
    X
    X
    Clock Setup Valid
    n+2
    X
    X
    X
    X
    X
    X
    L
    Q
    0
    Contents of Address A
    0
    Read Out
    4875 tbl 13
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