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參數(shù)資料
| 型號(hào)： | IDT71V256SA15PZG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Lower Power 3.3V CMOS Fast SRAM 256K (32K x 8-Bit) |
| 中文描述： | 32K X 8 CACHE SRAM, 15 ns, PDSO28 |
| 封裝： | ROHS COMPLIANT, TSOP1-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 482K |
| 代理商： | IDT71V256SA15PZG8 |
6
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,4,6)
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1,2,3,4)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured fromthe earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified t
WP.
CS
DATA
IN
ADDRESS
WE
WR
t
3101 drw 10
t
AW
t
DW
t
WC
t
CW
t
DH
AS
t
(5)
DATA VALID
,
NOTES:
1. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
2. t
WR
is measured fromthe earlier of
CS
or
WE
going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
6. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified t
WP.
CS
DATA
IN
ADDRESS
WE
DATA
OUT
OE
3101 drw 09
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
(3)
(6)
t
AS
(5)
(3)
t
OHZ
(5)
DATA VALID
(5)
,
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V256SA15PZGI | 功能描述:IC SRAM 256KBIT 15NS 28TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| IDT71V256SA15PZGI8 | 功能描述:IC SRAM 256KBIT 15NS 28TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
| IDT71V256SA15PZI | 功能描述:IC SRAM 256KBIT 15NS 28TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V256SA15PZI8 | 功能描述:IC SRAM 256KBIT 15NS 28TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V256SA15TP | 制造商:Integrated Device Technology Inc 功能描述:Static RAM, 32Kx8, 28 Pin, Plastic, DIP |
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