參數(shù)資料
型號: IDT71V256SA15Y
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT)
中文描述: 32K X 8 CACHE SRAM, 15 ns, PDSO28
封裝: 0.300 INCH, ROHS COMPLIANT, SOJ-28
文件頁數(shù): 2/6頁
文件大?。?/td> 67K
代理商: IDT71V256SA15Y
2
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
GND
V
CC
Commercial
0
°
C to +70
°
C
-40
°
C to +85
°
C
0V
3.3V
±
0.3V
3.3V
±
0.3V
Industrial
0V
3101 tbl 05
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
Rating
Value
Unit
V
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
–0.5 to +4.6
V
TERM
(2)
–0.5 to V
CC
+0.5
V
T
BIAS
T
STG
P
T
I
OUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
–55 to +125
–55 to +125
1.0
50
°
C
°
C
W
mA
3101 tbl 03
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output Capacitance
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
3101 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage - Inputs
2.0
5.0
V
V
IH
Input High Voltage - I/O
2.0
Vcc+0.3
V
V
IL
NOTE:
1. V
IL
(min.) = –2.0V for pulse width less than 5ns, once per cycle.
Input Low Voltage
–0.3
(1)
0.8
V
3101 tbl 06
TRUTH TABLE
(1)
WE
CS
OE
I/O
Function
Standby (ISB)
Standby (ISB1)
Output Disable
Read
Write
X
X
H
H
L
H
X
X
H
L
X
High-Z
High-Z
High-Z
D
OUT
D
IN
V
HC
L
L
L
NOTE:
1. H = V
IH
, L = V
IL
, X = Don’t Care
3101 tbl 02
3101 drw 02
5
6
7
8
9
10
11
12
13
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
24
23
22
21
20
19
18
17
16
15
SO28-5
P28-2
28
27
26
25
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
14
DIP/SOJ
TOP VIEW
PIN DESCRIPTIONS
Name
Description
A
0
–A
14
I/O
0
–I/O
7
CS
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
WE
OE
GND
V
CC
3101 tbl 01
TSOP
TOP VIEW
3101 drw 11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
SO28-8
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
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IDT71V256SA15YI LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT)
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