參數(shù)資料
型號(hào): IDT71V2577SA85PFI
廠商: Integrated Device Technology, Inc.
元件分類: 通用總線功能
英文描述: 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
中文描述: 128K的x 36256畝× 18 3.3同步SRAM的2.5VI / O的流量通過輸出脈沖計(jì)數(shù)器,單周期取消
文件頁數(shù): 18/22頁
文件大小: 304K
代理商: IDT71V2577SA85PFI
6.42
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
4877 drw 11
,
NOTES:
1. ZZ input is LOW,
ADV
and
OE
are HIGH, and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW
writes are shown, the functionality of
BWE
and
BW
x together is the same as
GW
.
4. For write cycles,
ADSP
and
ADSC
have different limtations.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW, BWE, BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
4877 drw 10
,
NOTES:
1. ZZ input is LOW,
ADV
is HIGH and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP
and
ADSC
function identically and are therefore interchangable.
相關(guān)PDF資料
PDF描述
IDT71V2577YS75BG 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2577YS75BGI 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2577YS75BQ 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2577YS75BQI 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
IDT71V2577YS75PF 128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
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