參數(shù)資料
型號: IDT71V2578S133BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
中文描述: 256K X 18 CACHE SRAM, 4.2 ns, PBGA165
封裝: FBGA-165
文件頁數(shù): 18/22頁
文件大?。?/td> 282K
代理商: IDT71V2578S133BQ
6.42
18
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW
,
BWE
,
BW
x
CE
,
CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
4876 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW,
ADV
is HIGH and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP
and
ADSC
function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW,
ADV
and
OE
are HIGH, and
LBO
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW
writes are shown, the functionality of
BWE
and
BW
x together is the same as
GW
.
4. For write cycles,
ADSP
and
ADSC
have different limtations.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE
,
CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
4876 drw 15
,
相關(guān)PDF資料
PDF描述
IDT71V2578S133BQI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2578S133PF 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2578YSA133BGI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2578YSA133BQ 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2578YSA133BQI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
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