參數(shù)資料
型號(hào)： IDT71V2578YS133BQI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
中文描述： 256K X 18 CACHE SRAM, 4.2 ns, PBGA165
封裝： FBGA-165
文件頁(yè)數(shù)： 1/22頁(yè)
文件大?。?/td> 282K
代理商： IDT71V2578YS133BQI
JUNE 2003
DSC-4876/09
1
2003 Integrated Device Technology, Inc.
Features
N
128K x 36, 256K x 18 memory configurations
N
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
N
LBO
input selects interleaved or linear burst mode
N
Self-timed write cycle with global write control (
GW
), byte write
enable (
BWE
), and byte writes (
BW
x)
N
3.3V core power supply
N
Power down controlled by ZZ input
N
2.5V I/O
N
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
N
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Description
The IDT71V2576/78 are high-speed SRAMs organized as 128K x
36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address
and control registers. Internal logic allows the SRAMto generate a self-
timed write based upon a decision which can be left until the end of the write
cycle.
The burst mode feature offers the highest level of performance to the
systemdesigner, as the IDT71V2576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address fromthe processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (
ADV
=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V2578.
A
0
-A
17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
N/A
V
SS
Ground
Supply
N/A
4876 tbl 01
128K X 36, 256K X 18
3.3V Synchronous SRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
IDT71V2576S
IDT71V2578S
IDT71V2576SA
IDT71V2578SA
相關(guān)PDF資料
PDF描述
IDT71V2576YSA133BQ 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2576YSA133BQI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2576YSA133PF 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2576YSA133PFI 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
IDT71V2576YSA150BG 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
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